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A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits., , and . IEEE Trans. Computers, 43 (6): 687-698 (1994)An histogram based procedure for current testing of active defects.. ITC, page 714-723. IEEE Computer Society, (1999)Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results., and . ITC, page 1019-1026. IEEE Computer Society, (1998)Tools for the Characterization of Bipolar CML Testability., , , , , and . VTS, page 388-395. IEEE Computer Society, (2001)Early Analysis of Soft Error Effects for Aerospace Applications Using Probabilistic Model Checking., , , and . FTSCS, volume 419 of Communications in Computer and Information Science, page 54-70. Springer, (2013)Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits., , and . IEEE Trans. Computers, 44 (5): 724-728 (1995)3DSDM: A 3 Data-Source Diagnostic Method., and . DFT, page 117-123. IEEE Computer Society, (2003)Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits., , , , , and . VTS, page 1-6. IEEE Computer Society, (2018)Circuit Level Modeling of Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiation., , , and . CoRR, (2015)On Delay Faults Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiations., , , , and . CoRR, (2014)