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Variable-Based Multi-module Data Caches for Clustered VLIW Processors.

, , , , and . IEEE PACT, page 207-217. IEEE Computer Society, (2005)

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AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures., , , , and . IEEE Trans. Computers, 58 (6): 770-783 (2009)Fast, Accurate and Flexible Data Locality Analysis., and . IEEE PACT, page 124-129. IEEE Computer Society, (1998)A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors., , and . IEEE PACT, page 175-184. IEEE Computer Society, (2001)Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors., , and . MICRO, page 315-325. IEEE Computer Society, (2003)Distributed Data Cache Designs for Clustered VLIW Processors., , and . IEEE Trans. Computers, 54 (10): 1227-1241 (2005)Analyzing Data Locality in Numeric Applications., and . IEEE Micro, 20 (4): 58-66 (2000)A locality sensitive multi-module cache with explicit management., and . International Conference on Supercomputing, page 51-59. ACM, (1999)Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices., , , , , , , and . IEEE Trans. Parallel Distributed Syst., 19 (7): 914-925 (2008)Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices., , , , , and . PLDI, page 269-279. ACM, (2005)Instruction scheduling for a clustered VLIW processor with a word-interleaved cache., , and . Concurr. Comput. Pract. Exp., 18 (11): 1391-1411 (2006)