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Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers.

, , , , and . ISCAS (1), page 345-348. IEEE, (2003)

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Novel recharge semi-floating-gate CMOS logic for multiple-valued systems., , , and . ISCAS (5), page 193-196. IEEE, (2003)A low-voltage sinc/sup 2/ decimator implemented by a new circuit technique using floating-gate MOS transistors., , , and . ISCAS (5), page 397-400. IEEE, (2002)Neuromorphic analog communication., , , and . ICNN, page 920-925. IEEE, (1996)Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers., , , , and . ISCAS (1), page 345-348. IEEE, (2003)Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion., , , and . ISCAS (4), page 838-841. IEEE, (2001)Extreme low-voltage floating-gate CMOS transconductance amplifier., , , , and . ISCAS (1), page 37-40. IEEE, (2001)Ultra low-voltage floating-gate transconductance amplifier., , and . ISCAS, page 347-350. IEEE, (2000)A novel floating-gate multiple-valued CMOS full-adder., , , , and . ISCAS (1), page 877-880. IEEE, (2002)Ultralow-voltage floating-gate analog multiplier with tunable linearity., , and . ISCAS, page 245-248. IEEE, (2000)Ultra low-voltage floating-gate transconductance amplifier with tunable gain and linearity., , and . ISCAS, page 343-346. IEEE, (2000)