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A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration.

G. Cardarilli, L. Carlo, A. Nannarelli, F. Pandolfi, and M. Re. ISSPIT, page 291-296. IEEE Computer Society, (2015)

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Alberto Fierro

Alberto Ricco

Alberto Moreira

Alberto Botti

Other publications of authors with the same name

Design of power efficient FPGA based hardware accelerators for financial applications.J. Hegner, J. Sindholt, and A. Nannarelli. NORCHIP, page 1-4. IEEE, (2012)Thermal aware floorplanning incorporating temperature dependent wire delay estimation.A. Winther, W. Liu, A. Nannarelli, and S. Vrudhula. Microprocess. Microsystems, 39 (8): 807-815 (2015)Guest Editorial: Special Section on Emerging and Impacting Trends on Computer Arithmetic.S. Oberman, L. Sousa, B. Pasca, and A. Nannarelli. IEEE Trans. Emerg. Top. Comput., 10 (3): 1239-1240 (2022)Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization.W. Liu, A. Calimera, A. Macii, E. Macii, A. Nannarelli, and M. Poncino. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (3): 406-418 (2013)Unified Digit Selection for Radix-4 Recurrence Division and Square Root.D. Harris, J. Stine, M. Ercegovac, A. Nannarelli, K. Parry, and C. Turek. IEEE Trans. Computers, 73 (1): 292-300 (January 2024)Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction.E. Antelo, P. Montuschi, and A. Nannarelli. IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (2): 409-418 (2017)On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters.G. Cardarilli, A. Nannarelli, and M. Re. VLSI-SoC (Selected Papers), volume 313 of IFIP Advances in Information and Communication Technology, page 174-190. Springer, (2008)An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm.S. Spanò, G. Cardarilli, L. Nunzio, R. Fazzolari, D. Giardino, M. Matta, A. Nannarelli, and M. Re. IEEE Access, (2019)Twenty years of research on RNS for DSP: Lessons learned and future perspectives.P. Albicocco, G. Cardarilli, A. Nannarelli, and M. Re. ISIC, page 436-439. IEEE, (2014)Power characterization of digital filters implemented on FPGA.G. Cardarilli, A. Re, A. Nannarelli, and M. Re. ISCAS (5), page 801-804. IEEE, (2002)

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Disambiguation of "Nannarelli, Alberto"

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A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration.

Please choose a person to relate this publication to

Alberto Fierro

Alberto Ricco

Alberto Moreira

Alberto Moreira

Alberto Botti

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Nannarelli, Alberto"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration.

Please choose a person to relate this publication to

Alberto Fierro

Alberto Ricco

Alberto Moreira

Alberto Moreira

Alberto Botti

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration.