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Disambiguation of "Otero, Andrés"

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Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs.

, , , , , , and . FPL, page 369-375. IEEE Computer Society, (2011)

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Lourdes Otero León

Concepción Otero Moreno

Andrés Kecskeméthy

Andrés Bejas

Andrés Kling

 

Other publications of authors with the same name

Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs., , , , and . IEEE Access, (2020)A scalable evolvable hardware processing array., , , , and . ReConFig, page 1-7. IEEE, (2013)FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework., , , , , and . Sensors, 18 (6): 1877 (2018)Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic., , , and . Microprocess. Microsystems, 38 (8): 899-910 (2014)Dynamically Reconfigurable Variable-precision Sparse-Dense Matrix Acceleration in Tensorflow Lite., , and . CoRR, (2023)Multi-grain reconfigurable and scalable overlays for hardware accelerator composition., , and . J. Syst. Archit., (2021)A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution., , and . ARC, volume 13569 of Lecture Notes in Computer Science, page 47-61. Springer, (2022)A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays., , , , , and . IPDPS Workshops, page 182-191. IEEE, (2013)Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs., , , , , , and . FPL, page 369-375. IEEE Computer Society, (2011)Generic Systolic Array for Run-Time Scalable Cores., , , and . ARC, volume 5992 of Lecture Notes in Computer Science, page 4-16. Springer, (2010)