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Towards an explanatory and computational theory of scientific discovery, , , , , and . CoRR, (2009)A high-speed, low-power 3D-SRAM architecture., , and . CICC, page 201-204. IEEE, (2008)A Verilog piecewise-linear analog behavior model for mixed-signal validation., and . CICC, page 1-5. IEEE, (2013)An Analytical Cache Model., , and . ACM Trans. Comput. Syst., 7 (2): 184-215 (1989)Tiny Tera: a packet switch core., , , , and . IEEE Micro, 17 (1): 26-33 (1997)Digital Analog Design: Enabling Mixed-Signal System Validation., , , , and . IEEE Des. Test, 32 (1): 44-52 (2015)Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models., and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (1): 23-33 (2016)A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs., , , , , , , , , and . DATE, page 846-851. IEEE, (2020)False coupling exploration in timing analysis., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (11): 1795-1805 (2005)Timing analysis including clock skew., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (11): 1608-1618 (1999)