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Disambiguation of "Choi, Joo-Sun"

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Silicon 3D-integration technology and systems.

, , , , , , , , , and . ISSCC, page 510-511. IEEE, (2010)

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Sun Choi

Sun Choi

Sun Choi

Sun Choi

Im-Joo Choi

 

Other publications of authors with the same name

17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)CMOS Charge Pump With No Reversion Loss and Enhanced Drivability., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (6): 1441-1445 (2014)An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme., , , , , , , and . ISSCC, page 410-411. IEEE, (2013)A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme., , , , , , , , , and 9 other author(s). ISSCC, page 44-46. IEEE, (2012)Silicon 3D-integration technology and systems., , , , , , , , , and . ISSCC, page 510-511. IEEE, (2010)An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface., , , , , , , and . ISSCC, page 136-138. IEEE, (2012)A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme., , , , , and . IEEE J. Solid State Circuits, 44 (8): 2222-2232 (2009)An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 42 (1): 193-200 (2007)A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation., , , , , , , , , and 10 other author(s). IEEE J. Solid State Circuits, 50 (1): 178-190 (2015)Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM., , , , , , and . DAC, page 91:1-91:6. ACM, (2015)