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Synthesis of functions and procedures in behavioral VHDL.

, , , and . EURO-DAC, page 560-565. IEEE Computer Society, (1993)

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Architectural tradeoffs in synthesis of pipelined controls., and . EURO-DAC, page 244-249. IEEE Computer Society, (1993)Synthesis of functions and procedures in behavioral VHDL., , , and . EURO-DAC, page 560-565. IEEE Computer Society, (1993)An Algorithm for Array Variable Clustering., , and . EDAC-ETC-EUROASIC, page 262-266. IEEE Computer Society, (1994)100-hour design cycle: a test case., , , , and . EURO-DAC, page 144-149. IEEE Computer Society, (1994)High-Level Transformations for Minimizing Syntactic Variances., , and . DAC, page 413-418. ACM Press, (1993)Semantics and synthesis of signals in behavioral VHDL., , , and . EURO-DAC, page 616-621. IEEE Computer Society Press, (1992)System design methodologies: aiming at the 100 h design cycle., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 4 (1): 70-82 (1996)Introduction to High-Level Synthesis., and . IEEE Des. Test Comput., 11 (4): 44-54 (1994)An Algorithm for Component Selection in Performance Optimized Scheduling., and . ICCAD, page 92-95. IEEE Computer Society, (1991)