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Chip-level and multi-node analysis of energy-optimized lattice Boltzmann CFD simulations.

, , , , and . Concurr. Comput. Pract. Exp., 28 (7): 2295-2315 (2016)

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RZBENCH: Performance evaluation of current HPC architectures using low-level and application benchmarks, , , and . CoRR, (2007)Benchmark Analysis and Application Results for Lattice Boltzmann Simulations on NEC SX Vector and Intel Nehalem Systems., , and . Parallel Process. Lett., 19 (4): 491-511 (2009)CRAFT: A Library for Easier Application-Level Checkpoint/Restart and Automatic Fault Tolerance., , , , , and . IEEE Trans. Parallel Distributed Syst., 30 (3): 501-514 (2019)An Evaluation of Different I/O Techniques for Checkpoint/Restart., , , , and . IPDPS Workshops, page 1708-1716. IEEE, (2013)Asynchronous MPI for the Masses, , , and . CoRR, (2013)Efficient Temporal Blocking for Stencil Computations by Multicore-Aware Wavefront Parallelization., , , , and . COMPSAC (1), page 579-586. IEEE Computer Society, (2009)An analysis of energy-optimized lattice-Boltzmann CFD simulations from the chip to the highly parallel level, , , and . CoRR, (2013)Vector Computers in a World of Commodity Clusters, Massively Parallel Systems and Many-Core Many-Threaded CPUs: Recent Experience Based on an Advanced Lattice Boltzmann Flow Solver., , and . High Performance Computing in Science and Engineering, Springer, (2008)Comparison of different propagation steps for lattice Boltzmann methods., , , and . Comput. Math. Appl., 65 (6): 924-935 (2013)Asynchronous Checkpointing by Dedicated Checkpoint Threads., , , and . EuroMPI, volume 7490 of Lecture Notes in Computer Science, page 289-290. Springer, (2012)