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Estimation of BIST Resources During High-Level Synthesis., , and . J. Electron. Test., 13 (3): 221-237 (1998)Aliasing Probability for Multiple Input Signature Analyzer., , and . IEEE Trans. Computers, 39 (4): 586-591 (1990)An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation., , and . IEEE Trans. Computers, 57 (3): 375-388 (2008)BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms., and . IEEE Trans. Computers, 45 (3): 257-269 (1996)Defect and Error Tolerance in the Presence of Massive Numbers of Defects., , and . IEEE Des. Test Comput., 21 (3): 216-227 (2004)Benefits of a SoC-Specific Test Methodology., , and . IEEE Des. Test Comput., 20 (3): 68-77 (2003)Analytical models for crosstalk excitation and propagation in VLSI circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (10): 1117-1131 (2002)Improving the Practical Space and Time Efficiency of the Shortest-Paths Approach to Sum-of-Pairs Multiple Sequence Alignment., , and . J. Comput. Biol., 2 (3): 459-472 (1995)On Generating Vectors That Invoke High Circuit Delays - Delay Testing and Dynamic Timing Analysis., and . ATS, page 485-492. IEEE, (2007)Accurate modeling and fault simulation of Byzantine resistive bridges., and . ICCD, page 347-353. IEEE, (2007)