Author of the publication

A SISO Register Circuit Tailored for Input Data with Low Transition Probability.

, , , , , and . IEEE Trans. Computers, 66 (1): 45-51 (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

High-speed direct digital frequency synthesizers in 0.25-μm CMOS., , , and . CICC, page 163-166. IEEE, (2004)Fixed-width CSD multipliers with minimum mean square error., , , , , , and . ISCAS, page 4149-4152. IEEE, (2010)Efficient implementation of pseudochaotic piecewise linear maps with high digitization accuracies., , , , , and . I. J. Circuit Theory and Applications, 40 (1): 1-14 (2012)A high-speed differential resistor ladder., , and . Microelectron. J., 43 (6): 433-438 (2012)Efficient Logarithmic Converters for Digital Signal Processing Applications., , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (10): 667-671 (2011)Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (8): 1200-1209 (2016)Variable Latency Speculative Han-Carlson Adder., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (5): 1353-1361 (2015)Approximate Multipliers Based on New Approximate Compressors., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (12): 4169-4182 (2018)A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures., , , , , , , , , and 16 other author(s). CoRR, (2023)Booth folding encoding for high performance squarer circuits., and . IEEE Trans. Circuits Syst. II Express Briefs, 50 (5): 250-254 (2003)