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Disambiguation of "Rodrigues, Joachim Neves"

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Ultra low power transceivers for wireless sensors and body area networks.

, , , , , , , , , , , , and . ISMICT, page 1-5. IEEE, (2014)

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Fabio Schittler Neves

Jaroslav Neveselý

Sérgio Ricardo Neves Miranda

Patrícia Neves

Jairo Pereira Neves

 

Other publications of authors with the same name

A 65 nm single stage 28 fJ/cycle 0.12 to 1.2V level-shifter., and . ISCAS, page 990-993. IEEE, (2014)3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI., , , and . ISSCC, page 60-61. IEEE, (2017)A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS., , and . VLSI-SoC, page 253-258. IEEE, (2010)Algorithm and hardware aspects of pre-coding in massive MIMO systems., , , and . ACSSC, page 1144-1148. IEEE, (2015)A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs., , , , , and . VLSI-SoC, page 380-385. IEEE, (2013)An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI., , , , and . A-SSCC, page 229-232. IEEE, (2016)Benchmarking of Standard-Cell Based Memories in the Sub- VT Domain in 65-nm CMOS Technology., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (2): 173-182 (2011)Ultra-Low-Power Error Correction Circuits: Technology Scaling and Sub-VT Operation., and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (12): 913-917 (2012)TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing., , , , , , and . VLSI-SoC, page 159-164. IEEE, (2012)A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS., , , , , and . ESSCIRC, page 321-324. IEEE, (2012)