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Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS., , and . NORCHIP, page 1-4. IEEE, (2011)Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain., , , , and . ISCAS, page 837-840. IEEE, (2011)Supply-voltage down conversion for digital CMOS designs., , , and . ICECS, page 339-342. IEEE, (2014)Ultra low energy design exploration of digital decimation filters in 65 nm dual-VT CMOS in the sub-VT domain., , , , and . Microprocess. Microsystems, 37 (4-5): 494-504 (2013)Reduction of Substrate Noise in Sub Clock Frequency Range., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (6): 1287-1297 (2010)A digital baseband for low power FSK based receiver in 65 nm CMOS., , and . ICECS, page 159-162. IEEE, (2014)Benchmarking of Standard-Cell Based Memories in the Sub- VT Domain in 65-nm CMOS Technology., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (2): 173-182 (2011)Power savings in digital filters for wireless communication., , and . ECCTD, page 1-4. IEEE, (2013)A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS., , , , , and . ESSCIRC, page 321-324. IEEE, (2012)A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS., , , and . ICECS, page 448-451. IEEE, (2012)