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Power Reduction in VLIW Processor with Compiler Driven Bypass Network., , and . VLSI Design, page 233-238. IEEE Computer Society, (2007)Front-End Design Flows for Systems on Chip: An Embedded Tutorial., and . VLSI Design, page 417-422. IEEE Computer Society, (2010)An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform., and . ISCAS, page 1377-1380. IEEE, (2007)Energy efficient data flow transformation for Givens Rotation based QR Decomposition., , , , and . DATE, page 1-4. European Design and Automation Association, (2014)Exploiting temporal decoupling to accelerate trace-driven NoC emulation., , , and . CODES+ISSS, page 315-324. ACM, (2011)Rank based dynamic voltage and frequency scaling fortiled graphics processors., , and . CODES+ISSS, page 3-12. ACM, (2010)Exploration of Loop Unroll Factors in High Level Synthesis., , , , and . VLSI Design, page 465-466. IEEE Computer Society, (2018)Memory Architectures.. Handbook of Hardware/Software Codesign, Springer, (2017)SystemC: A Modeling Platform Supporting Multiple Design Abstractions.. ISSS, page 75-80. ACM / IEEE Computer Society, (2001)Estimating the Complexity of Synthesized Designs from FSM Specifications., , and . IEEE Des. Test Comput., 10 (1): 30-35 (1993)