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I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs.

, , , , , , , and . ASP-DAC, page 151-156. IEEE, (2013)

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Small delay testing for TSVs in 3-D ICs., , , , , , and . DAC, page 1031-1036. ACM, (2012)Enabling inter-die co-optimization in 3-D IC with TSVs., , , , and . VLSI-DAT, page 1-4. IEEE, (2013)A SAR ADC missing-decision level detection and removal technique., , , and . VTS, page 31-36. IEEE Computer Society, (2012)Temperature-aware online testing of power-delivery TSVs., , , and . 3DIC, page TS10.3.1-TS10.3.6. IEEE, (2015)Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (5): 737-747 (2013)In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (3): 443-453 (2013)Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (9): 2343-2351 (2013)Time-to-Digital Converter Compiler for On-Chip Instrumentation., , , and . IEEE Des. Test, 37 (4): 101-107 (2020)A built-in self-test scheme for 3D RAMs., , , , , , and . ITC, page 1-9. IEEE Computer Society, (2012)An FPGA-based test platform for analyzing data retention time distribution of DRAMs., , , , , and . VLSI-DAT, page 1-4. IEEE, (2013)