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Disambiguation of "Narayanan, Pritish"

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Hybrid Graphene Nanoribbon-CMOS tunneling volatile memory fabric.

, , , , , and . NANOARCH, page 189-195. IEEE Computer Society, (2011)

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Pritish Sinha

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

 

Other publications of authors with the same name

Equivalent-accuracy accelerated neural-network training using analogue memory., , , , , , , , , and 4 other author(s). Nat., 558 (7708): 60-67 (2018)A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh., , , , , , , , , and 5 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 31 (1): 114-127 (2023)Overview of the IBM Neural Computer Architecture., , , , , , and . CoRR, (2020)Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory., , , , , , and . IBM J. Res. Dev., 61 (4-5): 11:1-11:11 (2017)Towards a framework for designing applications onto hybrid nano/CMOS fabrics., , , , , , and . Microelectron. J., 40 (4-5): 656-664 (2009)Parameter variation sensing and estimation in nanoscale fabrics., , , , and . J. Parallel Distributed Comput., 74 (6): 2504-2511 (2014)An analog-AI chip for energy-efficient speech recognition and transcription., , , , , , , , , and 14 other author(s). Nat., 620 (7975): 768-775 (2023)CMOS Control Enabled Single-Type FET NASIC., , , and . ISVLSI, page 191-196. IEEE Computer Society, (2008)Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges., , , , , , , , , and . IRPS, page 1-10. IEEE, (2020)Validating cascading of crossbar circuits with an integrated device-circuit exploration., , , and . NANOARCH, page 37-42. IEEE Computer Society, (2009)