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Reliability testing of high aspect ratio through silicon vias fabricated with atomic layer deposition barrier, seed layer and direct plating and material properties characterization of electrografted insulator, barrier and seed layer for 3-D integration.

, , , and . 3DIC, page 1-8. IEEE, (2010)

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Macroelectronics: Perspectives on Technology and Applications., , , , , , , , , and 14 other author(s). Proc. IEEE, 93 (7): 1239-1256 (2005)Reliability testing of high aspect ratio through silicon vias fabricated with atomic layer deposition barrier, seed layer and direct plating and material properties characterization of electrografted insulator, barrier and seed layer for 3-D integration., , , and . 3DIC, page 1-8. IEEE, (2010)Vias-last process technology for thick 2.5D Si interposers., , , and . 3DIC, page 1-4. IEEE, (2011)Fabrication of TSV-based silicon interposers., , , , , , and . 3DIC, page 1-6. IEEE, (2010)High density interconnect bonding of heterogeneous materials using non-collapsible microbumps at 10 μm pitch., , , , , and . 3DIC, page 1-5. IEEE, (2013)Wafer-Level Vacuum Packaging of Smart Sensors., and . Sensors, 16 (11): 1819 (2016)Remote Crop Mapping at Scale: Using Satellite Imagery and UAV-Acquired Data as Ground Truth., , , , , , , and . Remote. Sens., 12 (12): 1984 (2020)Advanced 3D mixed-signal processor for infrared focal plane arrays: Fabrication and test., , , , , , , and . 3DIC, page 1-7. IEEE, (2014)Innovative practices on design & test for flexible hybrid electronics., , , and . VTS, page 1. IEEE Computer Society, (2018)