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Disambiguation of "Jr., Earl E. Swartzlander"

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Hardware Designs for Exactly Rounded Elemantary Functions.

, and . IEEE Trans. Computers, 43 (8): 964-973 (1994)

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Other publications of authors with the same name

A parallel implementation of the 2-D discrete wavelet transform without interprocessor communications., , and . IEEE Trans. Signal Process., 47 (11): 3179-3184 (1999)A pipelined architecture for the multidimensional DFT., and . IEEE Trans. Signal Process., 49 (9): 2096-2102 (2001)A scaled DCT architecture with the CORDIC algorithm., and . IEEE Trans. Signal Process., 50 (1): 160-167 (2002)A Variable-Latency Architecture for Accelerating Deterministic Approaches to Stochastic Computing., and . ACSSC, page 608-613. IEEE, (2019)VLSI Concurrent Error Correcting Adders and Multipliers., and . DFT, page 287-294. IEEE Computer Society, (1993)A Spanning Tree Carry Lookahead Adder., and . IEEE Trans. Computers, 41 (8): 931-939 (1992)A systolic array for 2-D DFT and 2-D DCT., and . ASAP, page 123-131. IEEE, (1994)Parallel Counters.. IEEE Trans. Computers, 22 (11): 1021-1024 (1973)A Fused Floating-Point Three-Term Adder., and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (10): 2842-2850 (2014)Calculators.. IEEE Ann. Hist. Comput., 17 (3): 75-77 (1995)