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Edit distance based instruction merging technique to improve flexibility of custom instructions toward flexible accelerator design., , and . ASP-DAC, page 219-224. IEEE, (2014)An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 98-589. IEEE, (2007)Learning-Based Power Modeling of System-Level Black-Box IPs., , , , , and . ICCAD, page 847-853. IEEE, (2015)Design of a low power SoC testchip for wearables and IoTs., , , , , , , and . Hot Chips Symposium, page 1-27. IEEE, (2015)Keynote talk II: Designing tomorrow's chips.. MEMOCODE, page 75-76. IEEE, (2013)High level design for wearables and IoT., and . ICCAD, page 72. IEEE, (2014)A 5-GHz Mesh Interconnect for a Teraflops Processor., , , , and . IEEE Micro, 27 (5): 51-61 (2007)Automatic generation of custom SIMD instructions for Superword Level Parallelism., and . DATE, page 1-6. European Design and Automation Association, (2014)Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives, , , , and . IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 28 (1): 3-21 (January 2009)Coverage Estimation for Symbolic Model Checking., , , and . DAC, page 300-305. ACM Press, (1999)