( en | de | ru )

 

Disambiguation of "Lin, Rung-Bin"

Author of the publication

copydeleteadd this publication to your clipboard
Clock gating optimization with delay-matching.

, and . DATE, page 643-648. IEEE, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Bin Lin

Alois Rung

Christoph Rung

Thomas Rung

Thomas Rung

 

Other publications of authors with the same name

Multi-layer constrained via minimization with conjugate conflict continuation graphs., and . ISCAS (4), page 525-528. IEEE, (2004)Multiple project wafers for medium-volume IC production., and . ISCAS (5), page 4725-4728. IEEE, (2005)Fuzzy logic approach to VLSI placement., , and . IEEE Trans. Very Large Scale Integr. Syst., 2 (4): 489-501 (1994)Comments on "Filling algorithms and analyses for layout density control".. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (10): 1209-1211 (2002)Variable-sized object packing and its applications to instruction cache design.. Comput. Electr. Eng., 34 (5): 438-444 (2008)Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs., , and . ACM Great Lakes Symposium on VLSI, page 37-42. ACM, (2011)Overview of the 2016 CAD contest at ICCAD., , , and . ICCAD, page 38. ACM, (2016)Weight-Based Bus-Invert Coding for Low-Power Applications., and . ASP-DAC/VLSI Design, page 121-125. IEEE Computer Society, (2002)Reticle Exposure Plans for Multi-Project Wafers., , , and . DDECS, page 341-344. IEEE Computer Society, (2007)Simultaneous transistor pairing and placement for CMOS standard cells., , , , , , and . DATE, page 1647-1652. ACM, (2015)