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Energy efficient routing techniques with guaranteed reliability based on multi-level uncertain graph.

, , , , and . RTCSA, page 1-9. IEEE Computer Society, (2014)

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An Integrated Framework of Design Optimization and Space Minimization for DSP applications., , and . ISCAS (5), page 601-604. IEEE, (2003)Performance optimization of multiple memory architectures for DSP., , and . ISCAS (5), page 469-472. IEEE, (2002)Partitioning and Retiming of Multi-Dimensional Systems., , and . ISCAS, page 227-230. IEEE, (1994)Communication Scheduling With Re-Routing Based On Static And Hybrid Techniques., , and . Journal of Circuits, Systems, and Computers, 13 (5): 1039-1064 (2004)Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping., , and . VLSI Signal Processing, 47 (2): 153-167 (2007)Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors., , , and . IJHPCN, 1 (1/2/3): 4-16 (2004)General loop fusion technique for nested loops considering timing and code size., , , and . CASES, page 190-201. ACM, (2004)2011 ACM TODAES best paper award., and . ACM Trans. Design Autom. Electr. Syst., 16 (4): 36:1 (2011)Loop scheduling with timing and switching-activity minimization for VLIW DSP., , , , and . ACM Trans. Design Autom. Electr. Syst., 11 (1): 165-185 (2006)Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation., , , , , and . DAC, page 350-355. ACM, (2010)