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Automatic dsp cache memory management and fast prototyping for multiprocessor image applications.

, , , and . EUSIPCO, page 1-5. IEEE, (2006)

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Fast Prototyping Methodology for Distributed and Heterogeneous Architectures: Application to Mpeg-4 Video Tools., , and . Des. Autom. Embed. Syst., 9 (2): 141-154 (2004)A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore., , , and . HPEC, page 1-7. IEEE, (2018)A comparison of stereo matching algorithms on multi-core Digital Signal Processor platform., , , and . 3D Image Processing, Measurement (3DIPM), and Applications, page 49-54. Society for Imaging Science and Technology, (2017)Automated Clustering and Pipelining of Dataflow Actors for Controlled Scheduling Complexity., , , and . EUSIPCO, page 1698-1702. IEEE, (2023)Design Space Exploration for Memory-Oriented Approximate Computing Techniques., , and . ASAP, page 122-125. IEEE, (2022)Implementation of a Fast Fourier transform algorithm onto a manycore processor., , , and . DASIP, page 1-7. IEEE, (2015)A dedicated lightweight binocular stereo system for real-time depth-map generation., , , , , and . DASIP, page 215-221. IEEE, (2016)Optimization of Calibration Algorithms on a Manycore Embedded Platform., , , and . SiPS, page 164-169. IEEE, (2018)A VsynDEx Methodology for Fast Prototyping of Multi-C6x DSP Architectures., , , and . PDPTA, page 1507-1513. CSREA Press, (2002)OpenVVC Decoder Parameterized and Interfaced Synchronous Dataflow (PiSDF) Model: Tile Based Parallelism., , , , and . J. Signal Process. Syst., 95 (7): 895-907 (July 2023)