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40 Gb/s FPGA implementation of a reduced complexity volterra DFE for DQPSK optical links., , , , , and . ICTON, page 1-4. IEEE, (2015)Task graph mapping and scheduling on heterogeneous architectures under communication constraints., , , , and . SAMOS, page 239-244. IEEE, (2017)FPGA Implementations for Volterra DFEs., and . Panhellenic Conference on Informatics, page 23:1-23:5. ACM, (2014)A Hybrid ILP-CP Model for Mapping Directed Acyclic Task Graphs to Multicore Architectures., , , and . IPDPS Workshops, page 176-182. IEEE Computer Society, (2014)A Logic-Based Benders Decomposition Approach for Mapping Applications on Heterogeneous Multicore Platforms., , , and . ACM Trans. Embed. Comput. Syst., 15 (1): 19:1-19:28 (2016)Static Mapping of Applications on Heterogeneous Multi-Core Platforms Combining Logic-Based Benders Decomposition with Integer Linear Programming., , , and . ACM Trans. Design Autom. Electr. Syst., 23 (2): 26:1-26:24 (2018)A Multi-stage Hybrid Approach for Mapping Applications on Heterogeneous Multi-core Platforms., , , and . VLSI-SoC, page 1-6. IEEE, (2022)A hybrid approach for mapping and scheduling on heterogeneous multicore systems., , , and . SAMOS, page 360-365. IEEE, (2016)High-performance FPGA implementations of volterra DFEs for optical fiber systems., , and . ReConFig, page 1-8. IEEE, (2014)Mapping DAGs on Heterogeneous Platforms Using Logic-Based Benders Decompostion., , , and . ISVLSI, page 119-124. IEEE Computer Society, (2015)