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In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking.

, , and . IEEE Des. Test, 32 (6): 87-98 (2015)

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Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation., , , and . Proc. IEEE, 94 (12): 2109-2138 (2006)Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation., , , , , , , , and . IEICE Trans. Electron., 96-C (6): 884-893 (2013)Session 20 overview: Energy harvesting and SC power conversion: Analog subcommittee., and . ISSCC, page 356-357. IEEE, (2015)High Throughput/Gate AES Hardware Architectures Based on Datapath Compression., , , , , , , , , and . IEEE Trans. Computers, 69 (4): 534-548 (2020)Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (2): 440-447 (2010)Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2516-2523 (2013)High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition., , and . IEICE Trans. Electron., 88-C (10): 2001-2008 (2005)Chip-Level Substrate Coupling Analysis with Reference Structures for Verification., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (12): 2651-2660 (2007)Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation., , , , , and . IEICE Trans. Electron., 95-C (4): 586-593 (2012)Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (12): 2284-2291 (2012)