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pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

C. Lee, Y. Eom, J. Park, J. Lee, H. Kim, K. Kim, Y. Choi, H. Chang, J. Kim, J. Bang, S. Shin, H. Park, S. Park, Y. Choi, H. Lee, K. Jeon, J. Lee, H. Ahn, K. Kim, J. Kim, S. Chang, H. Hwang, D. Kim, Y. Yoon, S. Hyun, J. Park, Y. Song, Y. Park, H. Kwon, S. Bae, T. Oh, I. Song, Y. Bae, J. Choi, K. Park, S. Jang, and G. Jin. ISSCC, page 390-391. IEEE, (2017)

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Chul-Hoon Lee

Song Hoon Lee

Jae-Hoon Lee

Tae-Hoon Lee

Jeong-Hoon Lee

Other publications of authors with the same name

A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 µm CMOS A/D Converter for 3G Communication Systems.Y. Kim, K. Lee, M. Lee, and S. Lee. IEICE Trans. Electron., 92-C (9): 1194-1200 (2009)Cross-eye Jamming System with Effective Cross-Eye Gain by the Phase and Gain Control.J. Lee, J. Jo, C. Lee, and C. Lee. ICTC, page 1498-1500. IEEE, (2021)A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems.Y. Cho, K. Lee, H. Choi, Y. Kim, K. Moon, S. Lee, S. Hyun, and S. Park. APCCAS, page 339-342. IEEE, (2006)Provision of the Personalized Social Network Service Based on the Locality/Sociality Relations.J. Kim, J. Lee, H. Lee, and E. Paik. ICIW, page 235-238. IEEE Computer Society, (2009)A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter.K. Lee, Y. Cho, H. Choi, Y. Park, D. Sa, Y. Kim, and S. Lee. APCCAS, page 351-354. IEEE, (2006)SENSATION: A New Environment for Automatic Circuit Optimization and Statistical Analysis.Y. Kim, J. Lee, K. Kim, and S. Lee. ISCAS, page 1797-1801. IEEE, (1993)A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched-bias power-reduction techniques.H. Choi, Y. Kim, K. Lee, Y. Kim, and S. Lee. I. J. Circuit Theory and Applications, 37 (9): 955-967 (2009)A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers.Y. Kim, H. Choi, K. Lee, G. Ahn, S. Lee, J. Kim, K. Moon, M. Choi, K. Moon, H. Park and 1 other author(s). CICC, page 271-274. IEEE, (2009)A 10b 120MS/s 45nm CMOS ADC using A re-configurable three-stage switched op-amp.Y. Kim, K. Lee, S. Ji, Y. Kwon, S. Lee, K. Moon, M. Choi, H. Park, and B. Park. CICC, page 1-4. IEEE, (2010)A noise-immune stylus analog front-end using adjustable frequency modulation and linear-interpolating data reconstruction for both electrically coupled resonance and active styluses.K. Lee, S. Nam, J. Lee, M. Choi, H. Ko, S. Byun, J. chul Lee, Y. Lee, Y. Rhee, Y. Choi and 4 other author(s). ISSCC, page 184-186. IEEE, (2018)

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23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

Please choose a person to relate this publication to

Chul-Hoon Lee

Song Hoon Lee

Jae-Hoon Lee

Tae-Hoon Lee

Jeong-Hoon Lee

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lee, Hoon"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

Please choose a person to relate this publication to

Chul-Hoon Lee

Song Hoon Lee

Jae-Hoon Lee

Tae-Hoon Lee

Jeong-Hoon Lee

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.