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Disambiguation of "Virazel, Arnaud"

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Microprocessor Testing: Functional Meets Structural Test.

, , , , , and . J. Circuits Syst. Comput., 26 (8): 1740007:1-1740007:18 (2017)

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Arnaud Mende

Arnaud Moris

Julien Arnaud

Arnaud Dewalque

Arnaud Casteigts

 

Other publications of authors with the same name

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles., , , , and . VLSI-SoC, volume 240 of IFIP, page 267-281. Springer, (2005)Random Adjacent Sequences: An Efficient Solution for Logic BIST., , , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 413-424. Kluwer, (2001)A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction., , , , , , , , and . European Test Symposium, page 81-86. IEEE Computer Society, (2010)Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes., , , , , , and . European Test Symposium, page 132-137. IEEE Computer Society, (2010)On hardware generation of random single input change test sequences., , , , and . ETW, page 117-123. IEEE Computer Society, (2001)Intra-Cell Defects Diagnosis., , , , , , and . J. Electron. Test., 30 (5): 541-555 (2014)Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (5): 958-970 (2013)An efficient hybrid power modeling approach for accurate gate-level power estimation., , , , and . ICM, page 17-20. IEEE, (2015)A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing., , , , , and . ETS, page 1-4. IEEE, (2022)Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test., , , , , and . J. Electron. Test., 21 (2): 169-179 (2005)