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Model checking unbounded concurrent lists.

, , and . Int. J. Softw. Tools Technol. Transf., 18 (4): 375-391 (2016)

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System Level Design: Orthogonolization of Concerns and Platform-Based Design, , , , and . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (December 2000)Certified Timing Verification and the Transition Delay of a Logic Circuit., , , and . DAC, page 549-555. IEEE Computer Society Press, (1992)Exploiting Retiming in a Guided Simulation Based Validation Methodology., , and . CHARME, volume 1703 of Lecture Notes in Computer Science, page 350-353. Springer, (1999)On Solving the Partial MAX-SAT Problem., and . SAT, volume 4121 of Lecture Notes in Computer Science, page 252-265. Springer, (2006)Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation., and . CP, volume 2470 of Lecture Notes in Computer Science, page 200-215. Springer, (2002)A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal Processors., and . The Compiler Design Handbook, 2nd ed., CRC Press, (2007)Specification and encoding of transaction interaction properties., , and . Formal Methods Syst. Des., 39 (2): 144-164 (2011)PPU: A Control Error-Tolerant Processor for Streaming Applications with Formal Guarantees., , , , and . ACM J. Emerg. Technol. Comput. Syst., 13 (3): 43:1-43:29 (2017)CNNFlow: Memory-driven Data Flow Optimization for Convolutional Neural Networks., and . ACM Trans. Design Autom. Electr. Syst., 28 (3): 40:1-40:36 (2023)Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface., , , , , , , , , and 3 other author(s). ACM Trans. Design Autom. Electr. Syst., 29 (2): 35:1-35:25 (March 2024)