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A formally verified sequentializer for lustre-like concurrent synchronous data-flow programs.

, , , , , and . ICSE (Companion Volume), page 109-111. IEEE Computer Society, (2017)

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A fault tolerant interconnection network using error correcting codes., , and . ICPP, page 123-125. IEEE Computer Society, (1982): Data Prefetching In Shared Memory Multiprocessors., , and . ICPP, page 28-31. Pennsylvania State University Press, (1987)New Attacks and Defenses for Randomized Caches., , , and . CoRR, (2019)CIM: A Reliable Metric for Evaluating Program Phase Classifications., , , , , and . IEEE Comput. Archit. Lett., 6 (1): 9-12 (2007)Integrating Parallelizing Compilation Technology and Processor Architecture for Cost-Effective Concurrent multithreading., , , , , , , and . J. Inf. Sci. Eng., 14 (1): 205-222 (1998)Distributing Hot-Spot Addressing in Large-Scale Multiprocessors., , and . IEEE Trans. Computers, 36 (4): 388-395 (1987)An Empirical Study on Array Subscripts and Data Dependencies., , and . ICPP (2), page 145-152. Pennsylvania State University Press, (1989)0-271-00686-2.Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor., , , and . ACM Trans. Archit. Code Optim., 12 (1): 3:1-3:29 (2015)An Efficient Data Dependence Analysis for Parallelizing Compilers., , and . IEEE Trans. Parallel Distributed Syst., 1 (1): 26-34 (1990)Editorial.. IEEE Trans. Parallel Distributed Syst., 13 (1): 4 (2002)