( en | de | ru )

 

Disambiguation of "Yang, Seiyang"

Author of the publication

copydeleteadd this publication to your clipboard
A fast two-pass HDL simulation with on-demand dump.

, , , , , , , , , , and . ASP-DAC, page 422-427. IEEE, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

 

Other publications of authors with the same name

MULTES: Multilevel Temporal-Parallel Event-Driven Simulation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (6): 845-857 (2013)Simulation Acceleration with HW Re-Compilation Avoidance., , , and . VLSI Design, page 487-491. IEEE Computer Society, (2008)A fast two-pass HDL simulation with on-demand dump., , , , , , , , , and 1 other author(s). ASP-DAC, page 422-427. IEEE, (2008)Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (1): 4-12 (1991)Temporal parallel gate-level timing simulation., , , and . HLDVT, page 111-116. IEEE Computer Society, (2008)A new distributed event-driven gate-level HDL simulation by accurate prediction., , and . DATE, page 547-550. IEEE, (2011)PLA decomposition with generalized decoders., and . ICCAD, page 312-315. IEEE Computer Society, (1989)PLADE: a two-stage PLA decomposition., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (8): 943-954 (1992)Predictive parallel event-driven HDL simulation with a new powerful prediction strategy., , , , , , and . DATE, page 1-3. European Design and Automation Association, (2014)A new state assignment technique for testing and low power., , , and . DAC, page 510-513. ACM, (2004)