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A macrocell approach for VLSI processor design.

, , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (12): 1272-1277 (1988)

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A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC., , , , , , , , and . ITC, page 791-796. IEEE Computer Society, (1993)A next-generation 32-bit VLSI signal processor., , and . ICASSP, page 413-416. IEEE, (1986)A 40GOPS 250mW massively parallel processor based on matrix architecture., , , , , , , , , and 2 other author(s). ISSCC, page 1616-1625. IEEE, (2006)The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 42 (1): 183-192 (2007)A macrocell approach for VLSI processor design., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (12): 1272-1277 (1988)Built-in self-test in a 24 bit floating point digital signal processor., , , , , , and . ITC, page 880-885. IEEE Computer Society, (1990)Microarchitecture Support for Reducing Branch Penalty in a Supercscaler Processor., , , and . ICCD, page 208-216. IEEE Computer Society, (1996)