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Impact of III-V and Ge Devices on Circuit Performance., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (7): 1189-1200 (2013)Carbon nanotube transistor compact model for circuit design and performance optimization., , , and . JETC, 4 (2): 7:1-7:20 (2008)Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits., , , and . DAC, page 958-961. IEEE, (2007)Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement., , , , , , and . DAC, page 889-892. ACM, (2010)Interconnect scaling into the sub-10nm regime., , and . SLIP, page 2. ACM, (2012)Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via Patterning., , , and . ISPD, page 65-66. ACM, (2015)Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures., , , and . CoRR, (2015)Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs., , , , , , , and . IEEE J. Solid State Circuits, 49 (1): 190-201 (2014)High-density analog image storage in an analog-valued non-volatile memory array., , , , , , and . Neuromorph. Comput. Eng., 2 (4): 44018 (December 2022)Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (10): 1725-1736 (2008)