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Disambiguation of "Wu, Jui-Jen"

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A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques.

, , , , , , , , , , , and . VLSIC, page 112-113. IEEE, (2012)

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Jen-San Wu

Wu-Jen Chen

Jen-Jen Lin

Nicolas Juillet

Francis Juillerat

 

Other publications of authors with the same name

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme., , , , , , , , , and . IEEE J. Solid State Circuits, 49 (4): 908-916 (2014)A Differential Data-Aware Power-Supplied (D 2 AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications., , , , , , , and . IEEE J. Solid State Circuits, 45 (6): 1234-1245 (2010)34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices., , , , , , , , , and 5 other author(s). ISSCC, page 568-570. IEEE, (2024)A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices., , , , , , , , , and 8 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros., , , , , , and . IEEE J. Solid State Circuits, 50 (9): 2188-2198 (2015)Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 50 (11): 2786-2795 (2015)A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (11): 790-794 (2012)A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs., , , , , , , and . IEEE J. Solid State Circuits, 44 (4): 1209-1215 (2009)A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques., , , , , , , , , and 2 other author(s). VLSIC, page 112-113. IEEE, (2012)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (10): 2558-2569 (2013)