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A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques.

M. Chen, L. Chen, M. Chang, S. Yang, Y. Kuo, J. Wu, M. Ho, H. Su, Y. Chu, W. Wu, T. Yang, and H. Yamauchi. VLSIC, page 112-113. IEEE, (2012)

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Hua Yuan

Chi-Hua Chu

Chia-hua Chu

Li Yuan

Lei Yuan

Other publications of authors with the same name

Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.H. Huang, J. Wang, Y. Chu, T. Wu, K. Cheng, and C. Wu. ISCAS, page 1572-1575. IEEE, (1995)PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems.P. Wu, Y. Kuo, C. Wu, C. Chuang, Y. Chu, and W. Hwang. SoCC, page 136-139. IEEE, (2014)Collaborative voltage scaling with online STA and variable-latency datapath.T. Lin, P. Hsiao, C. Lin, S. Kuo, C. Lin, Y. Kuo, C. Liu, and Y. Chu. ACM Great Lakes Symposium on VLSI, page 347-352. ACM, (2010)Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells.S. Luo, K. Chang, M. Chen, C. Huang, Y. Chiu, P. Chen, L. Cheng, C. Liu, and Y. Chu. IEEE Trans. Circuits Syst. II Express Briefs, 61-II (12): 947-951 (2014)A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques.M. Chen, L. Chen, M. Chang, S. Yang, Y. Kuo, J. Wu, M. Ho, H. Su, Y. Chu, W. Wu and 2 other author(s). VLSIC, page 112-113. IEEE, (2012)A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range.M. Chen, M. Chang, P. Wu, Y. Kuo, C. Yang, Y. Chu, and W. Hwang. SoCC, page 92-97. IEEE, (2013)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques.M. Chang, M. Chen, L. Chen, S. Yang, Y. Kuo, J. Wu, H. Su, Y. Chu, W. Wu, T. Yang and 1 other author(s). IEEE J. Solid State Circuits, 48 (10): 2558-2569 (2013)A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme.J. Wu, Y. Chen, M. Chang, P. Chou, C. Chen, H. Liao, M. Chen, Y. Chu, W. Wu, and H. Yamauchi. IEEE J. Solid State Circuits, 46 (4): 815-827 (2011)Design of STR level converters for SoCs using the multi-island dual-VDD design technique.J. Wang, Y. Chang, C. Yeh, and Y. Chu. ISCAS, IEEE, (2006)An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation.M. Chen, M. Chang, Y. Chu, and W. Hwang. SoCC, page 5-10. IEEE, (2012)

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Disambiguation of "Chu, Yuan-Hua"

Please choose a person to relate this publication to

Hua Yuan

Chi-Hua Chu

Chia-hua Chu

Li Yuan

Lei Yuan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chu, Yuan-Hua"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques.

Please choose a person to relate this publication to

Hua Yuan

Chi-Hua Chu

Chia-hua Chu

Li Yuan

Lei Yuan

Other publications of authors with the same name

Disambiguation