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A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS.

, , , , , , and . IEEE J. Solid State Circuits, 52 (2): 448-459 (2017)

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General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators., and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (7): 506-510 (2014)A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique., , , , and . VLSIC, page 254-. IEEE, (2015)A 13bit 200MS/S pipeline ADC with current-mode MDACs., , , , , and . ISCAS, page 1-4. IEEE, (2017)A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques., , , , and . IEEE J. Solid State Circuits, 52 (6): 1591-1604 (2017)A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (4): 756-767 (2018)A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer., , , and . IEEE J. Solid State Circuits, 51 (6): 1398-1409 (2016)A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs., , , , , , , and . IEEE J. Solid State Circuits, 53 (11): 3280-3292 (2018)A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage., , , , and . IEEE J. Solid State Circuits, 52 (3): 657-668 (2017)An Ultra-Low Voltage Analog Front End for Strain Gauge Sensory System Application in 0.18 µm CMOS., and . IEICE Trans. Electron., 95-C (4): 733-743 (2012)A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 52 (2): 448-459 (2017)