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A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 52 (7): 1863-1875 (2017)Robust strategy synthesis for probabilistic systems applied to risk-limiting renewable-energy pricing., , and . EMSOFT, page 13:1-13:10. ACM, (2014)BAG: a designer-oriented integrated framework for the development of AMS circuit generators., , , , , , , , , and 3 other author(s). ICCAD, page 74-81. IEEE, (2013)Time-to-digital converter with 3-ps resolution and digital linearization algorithm., , , , and . ESSCIRC, page 262-265. IEEE, (2010)On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC., , , , , , , , and . A-SSCC, page 125-128. IEEE, (2016)Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC., , , , , , , , , and 4 other author(s). ESSCIRC, page 269-272. IEEE, (2016)Routing-Aware Design of Indoor Wireless Sensor Networks Using an Interactive Tool., , , and . IEEE Syst. J., 9 (3): 714-727 (2015)A routing-algorithm-aware design tool for indoor wireless sensor networks., , , and . ICNC, page 964-969. IEEE Computer Society, (2012)Formal Techniques for the Verification and Optimal Control of Probabilistic Systems in the Presence of Modeling Uncertainties.. University of California, Berkeley, USA, (2014)