Author of the publication

Factorization of Multi-Valued Logic Functions.

, , and . ISMVL, page 164-169. IEEE Computer Society, (1995)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Yield-award placement optimization for Switched-Capacitor analog integrated circuits., , , and . SoCC, page 170-173. IEEE, (2011)Is IDDQ testing not applicable for deep submicron VLSI in year 2011?, , , and . Asian Test Symposium, page 338-343. IEEE Computer Society, (2000)Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing., , and . Asian Test Symposium, page 324-329. IEEE Computer Society, (2005)Fanout fault analysis for digital logic circuits., , , and . Asian Test Symposium, page 33-39. IEEE Computer Society, (1995)Fault Analysis on Two-Level (K+1)-Valued Logic Circuits., , and . ISMVL, page 181-188. IEEE Computer Society, (1992)Nested Quantization Index Modulation for Reversible Watermarking and Its Application to Healthcare Information Management Systems., , , , and . Comput. Math. Methods Medicine, (2012)Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (2): 313-318 (2010)Complete Test Set for Multiple-Valued Logic Networks., , and . ISMVL, page 289-296. IEEE Computer Society, (1994)Functional test pattern generation for CMOS operational amplifier., , and . VTS, page 267-273. IEEE Computer Society, (1997)Yield evaluation of analog placement with arbitrary capacitor ratio., , and . ISQED, page 179-184. IEEE Computer Society, (2009)