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A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit.

F. Tachibana, O. Hirabayashi, Y. Takeyama, M. Shizuno, A. Kawasumi, K. Kushida, A. Suzuki, Y. Niki, S. Sasaki, T. Yabe, and Y. Unekawa. ISSCC, page 320-321. IEEE, (2013)

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Fumihiko Sato

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A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems.Y. Tsubouchi, D. Miyashita, Y. Satoh, T. Toi, F. Tachibana, M. Morimoto, J. Wadatsumi, and J. Deguchi. VLSI Circuits, page 149-150. IEEE, (2018)Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision.K. Nakata, A. Maki, D. Miyashita, F. Tachibana, T. Suzuki, and J. Deguchi. ISCAS, page 1. IEEE, (2019)A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems.Y. Tsubouchi, D. Miyashita, T. Toi, Y. Satoh, F. Tachibana, J. Wadatsumi, M. Morimoto, R. Fujimoto, and J. Deguchi. IEEE J. Solid State Circuits, 54 (4): 1086-1095 (2019)A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit.F. Tachibana, O. Hirabayashi, Y. Takeyama, M. Shizuno, A. Kawasumi, K. Kushida, A. Suzuki, Y. Niki, S. Sasaki, T. Yabe and 1 other author(s). ISSCC, page 320-321. IEEE, (2013)Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction.A. Kawasumi, Y. Takeyama, O. Hirabayashi, K. Kushida, F. Tachibana, Y. Niki, S. Sasaki, and T. Yabe. ICICDT, page 1-4. IEEE, (2012)FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision.A. Maki, D. Miyashita, K. Nakata, F. Tachibana, T. Suzuki, and J. Deguchi. A-SSCC, page 47-50. IEEE, (2018)A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit.F. Tachibana, O. Hirabayashi, Y. Takeyama, M. Shizuno, A. Kawasumi, K. Kushida, A. Suzuki, Y. Niki, S. Sasaki, T. Yabe and 1 other author(s). IEEE J. Solid State Circuits, 49 (1): 118-126 (2014)Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN.K. Nakata, D. Miyashita, A. Maki, F. Tachibana, S. Sasaki, J. Deguchi, and R. Fujimoto. AICAS, page 1-4. IEEE, (2021)A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access.K. Kushida, O. Hirabayashi, F. Tachibana, H. Hara, A. Kawasumi, A. Suzuki, Y. Takeyama, Y. Fujimura, Y. Niki, M. Shizuno and 2 other author(s). A-SSCC, page 161-164. IEEE, (2011)A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers.Y. Niki, A. Kawasumi, A. Suzuki, Y. Takeyama, O. Hirabayashi, K. Kushida, F. Tachibana, Y. Fujimura, and T. Yabe. IEEE J. Solid State Circuits, 46 (11): 2545-2551 (2011)

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Disambiguation of "Tachibana, Fumihiko"

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A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit.

Please choose a person to relate this publication to

Fumihiko Sato

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Disambiguation of "Tachibana, Fumihiko"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit.

Please choose a person to relate this publication to

Fumihiko Sato

Other publications of authors with the same name

Disambiguation

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A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit.