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TSV redundancy: Architecture and design issues in 3D IC.

, , , , , and . DATE, page 166-171. IEEE Computer Society, (2010)

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Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (12): 1686-1695 (2010)Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains., , , , , and . J. Supercomput., 42 (2): 201-223 (2007)A New Attack for Self-Certified Digital Signatures for E-commerce Applications., , , and . J. Inf. Sci. Eng., 37 (6): 1449-1466 (2021)Digital Secure-Communication Using Robust Hyper-Chaotic Systems., , , and . Int. J. Bifurc. Chaos, 18 (11): 3325-3339 (2008)A power-driven multiplication instruction-set design method for ASIPs., , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (1): 81-85 (2006)Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs., , , and . SoCC, page 236-241. IEEE, (2019)Layout Driven Selecting and Chaining of Partial Scan., , and . DAC, page 262-267. ACM Press, (1996)A Re-engineering Approach to Low Power FPGA Design Using SPFD., , and . DAC, page 722-725. ACM Press, (1998)Logic transformation for low-power synthesis., , , , and . ACM Trans. Design Autom. Electr. Syst., 7 (2): 265-283 (2002)Thermal-aware post compilation for VLIW architectures., and . ASP-DAC, page 606-611. IEEE, (2009)