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Disambiguation of "Ranganathan, N."

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VLSI Architectures for High-Speed Range Estimation.

, , and . IEEE Trans. Pattern Anal. Mach. Intell., 17 (9): 894-899 (1995)

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Hiranmayi Ranganathan

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N -L N Nguyen

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Other publications of authors with the same name

Simultaneous peak and average power minimization during datapath scheduling for DSP processors., , and . ACM Great Lakes Symposium on VLSI, page 215-220. ACM, (2003)A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks., , and . ACM Trans. Design Autom. Electr. Syst., 11 (3): 773-796 (2006)ACE: A VLSI Chip for Galois Field GF (2m) Based Exponentiation., and . VLSI Design, page 291-296. IEEE Computer Society, (1994)Power estimation of sequential circuits using hierarchical colored hardware petri net modeling., and . ISLPED, page 267-270. ACM, (2002)PANTHER: a parallel neuro-systolic architecture for real-time processing., and . ICNN, page 1006-1011. IEEE, (1996)trulla : An Algorithm For Path Planning Among Weighted Regions By Localized Propagations., , and . IROS, page 469-476. IEEE, (1992)Enhancing arithmetic and tree-based coding., , and . Inf. Process. Manag., 25 (3): 293-305 (1989)A VLSI systolic array processor chip for computing joins in a relational database., , and . Microprocess. Microsystems, 16 (5): 227-236 (1992)A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (1): 29-38 (2010)Timing-Based Placement Considering Uncertainty Due to Process Variations., and . IEEE Trans. Very Large Scale Integr. Syst., 18 (6): 1007-1011 (2010)