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A SystemC-based platform for assertion-based verification and mutation analysis in systems biology.

, , , , , , and . LATS, page 159-164. IEEE, (2016)

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Test Generation for Stuck-at and Gate-Delay Faults in Sequential Circuits: A Mixed Functional/Structural Method., , and . DFT, page 254-262. IEEE Computer Society, (1994)Implicit test generation for behavioral VHDL models., , and . ITC, page 587-596. IEEE Computer Society, (1998)An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems., , , , , , and . DATE, page 266-271. (2004)Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems., , and . Great Lakes Symposium on VLSI, page 118-123. IEEE Computer Society, (1997)Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip., , , , , and . ICCD, page 494-499. IEEE Computer Society, (2002)Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels., , , , , and . ICCD, page 654-658. IEEE Computer Society, (1997)SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation., , and . EUROMICRO, page 351-. IEEE Computer Society, (1996)Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions., , and . IEEE Trans. Computers, 60 (12): 1730-1743 (2011)An error simulation based approach to measure error coverage of formal properties., , , , , and . ACM Great Lakes Symposium on VLSI, page 53-58. ACM, (2002)A method to abstract RTL IP blocks into C++ code and enable high-level synthesis., , , and . DAC, page 156:1-156:9. ACM, (2013)