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Disambiguation of "Galy, Philippe"

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BIMOS transistor and its applications in ESD protection in advanced CMOS technology.

, , , , , , , , and . ICICDT, page 1-4. IEEE, (2012)

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Bernd Galyga

Henri Galy

Islam Galy Khalil

Benoît Philippe

Philippe Kersting

 

Other publications of authors with the same name

ESD protection using BIMOS transistor in 100 GHz RF application for advanced CMOS technology., , , , , , and . ICICDT, page 199-202. IEEE, (2013)A full characterization of single pitch IO ESD protection based on silicon controlled rectifier and dynamic trigger circuit in CMOS 32 nm node., , , , , and . Microelectron. Reliab., 51 (9-11): 1614-1617 (2011)Electro-thermal short pulsed simulation for SOI technology., , , , and . Microelectron. Reliab., 46 (9-11): 1482-1485 (2006)On the need for a new ESD verification methodology to improve the reliability of ICs in advanced 28nm UTBB FD-SOI technology., , , , and . Microelectron. Reliab., (2016)A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses., , , , , , , , , and . CoRR, (2023)Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K., , , , , , , , , and . IRPS, page 7. IEEE, (2022)6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology., , , , and . ICICDT, page 89-92. IEEE, (2013)Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies., , , , and . ICICDT, page 1-4. IEEE, (2017)Optimized in situ heating control on a new MOS device structure in 28nm UTBB FD-SOI CMOS technology., , and . ICICDT, page 157-160. IEEE, (2018)Computation of Self-Induced Magnetic Field Effects Including the Lorentz Force for Fast-Transient Phenomena in Integrated-Circuit Devices., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (6): 893-902 (2014)