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A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension.

, , , , , , , , and . IEEE Symposium on Computer Arithmetic, page 12-. IEEE Computer Society, (1999)

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High Speed Decimal Addition., and . IEEE Trans. Computers, 20 (8): 862-866 (1971)High-Speed Binary-to-Decimal Conversion.. IEEE Trans. Computers, 17 (5): 506-508 (1968)FPU Implementations with Denormalized Numbers., , and . IEEE Trans. Computers, 54 (7): 825-836 (2005)On Mod-2 Sums of Products.. IEEE Trans. Computers, 18 (10): 957 (1969)Minimum test patterns for residue networks., , , and . DAC, page 278-284. ACM, (1971)Series Approximation Methods for Divide and Square Root in the Power3(TM) Processor., , and . IEEE Symposium on Computer Arithmetic, page 116-123. IEEE Computer Society, (1999)P6 Binary Floating-Point Unit., , , and . IEEE Symposium on Computer Arithmetic, page 77-86. IEEE Computer Society, (2007)Avoiding Unknown States When Scanning Mutually Exclusive Latches., and . ITC, page 311-318. IEEE Computer Society, (1995)A Random-Walk Model of a Queue Storage Problem., and . IEEE Trans. Computers, 17 (11): 1093-1095 (1968)Leading Zero Anticipation and Detection-A Comparison of Methods., and . IEEE Symposium on Computer Arithmetic, page 7-12. IEEE Computer Society, (2001)