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Disambiguation of "Jain, Rinkle"

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Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator.

, , , , , , , , , , , and . IEEE J. Solid State Circuits, 51 (1): 18-30 (2016)

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Gora Jain

Prabhat Jain

Rajiv Jain

Himalaya Jain

Tushar Jain

 

Other publications of authors with the same name

A novel control technique to eliminate output-voltage-ripple in switched-capacitor DC-DC converters., and . ISCAS, page 825-828. IEEE, (2011)20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS., , , , , , , , , and . ISSCC, page 336-337. IEEE, (2017)Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS., , , , , and . CICC, page 1-4. IEEE, (2014)An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and $V_MIN$ Optimization., , , , , , , , , and 19 other author(s). IEEE J. Solid State Circuits, 54 (1): 144-157 (2019)A 2-Gb/s UWB Transceiver for Short-Range Reconfigurable FDD Wireless Networks., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 58 (5): 1285-1298 (May 2023)5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep., , , , , , , , , and 2 other author(s). ISSCC, page 108-109. IEEE, (2014)Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 51 (1): 18-30 (2016)A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer., , , , and . IEEE J. Solid State Circuits, 58 (4): 1002-1014 (2023)A 12MHz/38.4MHz Fast Start-Up Crystal Oscillator using Impedance Guided Chirp Injection in 22nm FinFET CMOS., , , , , , , , , and 1 other author(s). CICC, page 1-2. IEEE, (2021)A staircase conductance modulation scheme for input-current-shaping in switched-capacitor DC-DC converters., , and . ISCAS, page 1664-1667. IEEE, (2014)