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8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.

, , , , , , , , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)

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8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC., , , , , , , , and . A-SSCC, page 125-128. IEEE, (2016)A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI., , , , , and . ESSCIRC, page 153-162. IEEE, (2017)A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI., , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking., , , , , and . A-SSCC, page 69-72. IEEE, (2017)Resilient Low Voltage Accelerators for High Energy Efficiency., , , , , , , , and . HPCA, page 147-158. IEEE, (2019)A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI., , , , , and . IEEE J. Solid State Circuits, 53 (7): 2088-2100 (2018)