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Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.

T. Bao, D. Yakimets, J. Ryckaert, I. Ciofi, R. Baert, A. Veloso, J. Bömmels, N. Collaert, P. Roussel, S. Demuynck, P. Raghavan, A. Mercha, Z. Tokei, D. Verkest, A. Thean, and P. Wambacq. ESSDERC, page 102-105. IEEE, (2014)

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Edward Baert

Hendrik Rogier

Dietmar Rogier

Hermann Rogier

Rogier Blokland

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MPA: Parallelizing an Application onto a Multicore Platform Made Easy.J. Mignolet, R. Baert, T. Ashby, P. Avasare, H. Jang, and J. Son. IEEE Micro, 29 (3): 31-39 (2009)Exploring parallelizations of applications for MPSoC platforms using MPA.R. Baert, E. Brockmeyer, S. Wuytack, and T. Ashby. DATE, page 1148-1153. IEEE, (2009)Cell-Aware Test on Various Circuits in an Advanced 3-nm Technology.Z. Gao, M. Hu, R. Baert, B. Chehab, J. Swenton, S. Malagi, J. Huisken, K. Goossens, and E. Marinissen. IEEE Des. Test, 41 (2): 56-64 (2024)Application of Cell-Aware Test on an Advanced 3nm CMOS Technology Library.Z. Gao, S. Malagi, M. Hu, J. Swenton, R. Baert, J. Huisken, B. Chehab, K. Goossens, and E. Marinissen. ITC, page 1-6. IEEE, (2019)TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes.A. Mallik, P. Zuber, T. Liu, B. Chava, B. Ballal, P. Bario, R. Baert, K. Croes, J. Ryckaert, M. Badaroglu and 2 other author(s). DAC, page 24:1-24:6. ACM, (2013)An automatic scratch pad memory management tool and MPEG-4 encoder case study.R. Baert, E. de Greef, and E. Brockmeyer. DAC, page 201-204. ACM, (2008)Multi-Objective Genetic Algorithm for Task Assignment on Heterogeneous Nodes.C. del Notario, R. Baert, and M. D'Hondt. Int. J. Digit. Multim. Broadcast., (2012)Runtime Scheduling for Video Decoding on Heterogeneous Architectures.C. Blanch, R. Baert, P. Coene, M. D'Hondt, Z. Ma, and R. Wuyts. RTNS, page 195-204. (2011)Dedicated technology threshold voltage tuning for 6T SRAM beyond N7.M. Gupta, P. Weckx, S. Cosemans, P. Schuddinck, R. Baert, D. Jang, Y. Sherazi, P. Raghavan, A. Spessot, A. Mocuta and 1 other author(s). ICICDT, page 1-4. IEEE, (2017)Impact of device and interconnect process variability on clock distribution.N. Fievet, P. Raghavan, R. Baert, F. Robert, A. Mercha, D. Verkest, and A. Thean. ICICDT, page 1-4. IEEE, (2015)

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Disambiguation of "Baert, Rogier"

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Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.

Please choose a person to relate this publication to

Edward Baert

Hendrik Rogier

Dietmar Rogier

Hermann Rogier

Rogier Blokland

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Baert, Rogier"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.

Please choose a person to relate this publication to

Edward Baert

Hendrik Rogier

Dietmar Rogier

Hermann Rogier

Rogier Blokland

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.