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Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.

, , , , , , , , , , , , , , , and . ESSDERC, page 102-105. IEEE, (2014)

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Evaluation of via density and low-k Young's modulus influence on mechanical performance of advanced node multi-level Back-End-Of-Line., , , , , and . Microelectron. Reliab., (2016)Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies., , , , , , , , , and 6 other author(s). ESSDERC, page 102-105. IEEE, (2014)As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability., , , , , , , , , and 1 other author(s). Microelectron. Reliab., 54 (9-10): 1675-1679 (2014)Impact of process variability on BEOL TDDB lifetime model assessment., , , , and . IRPS, page 5. IEEE, (2015)Intrinsic reliability of local interconnects for N7 and beyond., , , , , , , , , and 1 other author(s). IRPS, page 2. IEEE, (2015)Design Technology co-optimization for N10., , , , , , , , , and 18 other author(s). CICC, page 1-8. IEEE, (2014)Constant voltage electromigration for advanced BEOL copper interconnects., , , , , , , and . IRPS, page 2. IEEE, (2015)Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects., , , , , , , , , and 1 other author(s). Microelectron. Reliab., (2017)Design considerations for the mechanical integrity of airgaps in nano-interconnects under chip-package interaction; a numerical investigation., , , , , and . Microelectron. Reliab., (2016)