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pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques.

R. Kho, D. Boursin, M. Brox, P. Gregorius, H. Hoenigschmid, B. Kho, S. Kieser, D. Kehrer, M. Kuzmenka, U. Moeller, P. Petkov, M. Plan, M. Richter, I. Russell, K. Schiller, R. Schneider, K. Swaminathan, B. Weber, J. Weber, I. Bormann, F. Funfrock, M. Gjukic, W. Spirkl, H. Steffens, J. Weller, and T. Hein. ISSCC, page 134-135. IEEE, (2009)

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Werner Jörg

Johannes-Richard Jörg

Edgar Jörg

Ole Berg Jörgensen

Erwin Jörg

Other publications of authors with the same name

23.1 An 8Gb 12Gb/s/pin GDDR5X DRAM for cost-effective high-performance applications.M. Brox, M. Balakrishnan, M. Broschwitz, C. Chetreanu, S. Dietrich, F. Funfrock, M. Gonzalez, T. Hein, E. Huber, D. Lauber and 19 other author(s). ISSCC, page 388-389. IEEE, (2017)An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling.T. Hollis, R. Schneider, M. Brox, T. Hein, W. Spirkl, M. Bach, M. Balakrishnan, S. Dietrich, F. Funfrock, M. Ivanov and 23 other author(s). IEEE J. Solid State Circuits, 57 (1): 224-235 (2022)A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques.R. Kho, D. Boursin, M. Brox, P. Gregorius, H. Hoenigschmid, B. Kho, S. Kieser, D. Kehrer, M. Kuzmenka, U. Moeller and 16 other author(s). IEEE J. Solid State Circuits, 45 (1): 120-133 (2010)An 8-Gb 12-Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications.M. Brox, M. Balakrishnan, M. Broschwitz, C. Chetreanu, S. Dietrich, F. Funfrock, M. Gonzalez, T. Hein, E. Huber, D. Lauber and 18 other author(s). IEEE J. Solid State Circuits, 53 (1): 134-143 (2018)75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques.R. Kho, D. Boursin, M. Brox, P. Gregorius, H. Hoenigschmid, B. Kho, S. Kieser, D. Kehrer, M. Kuzmenka, U. Moeller and 16 other author(s). ISSCC, page 134-135. IEEE, (2009)25.3 An 8Gb GDDR6X DRAM Achieving 22Gb/s/pin with Single-Ended PAM4 Signaling.T. Hollis, R. Schneider, M. Brox, T. Hein, W. Spirkl, M. Bach, M. Balakrishnan, S. Dietrich, F. Funfrock, M. Ivanov and 24 other author(s). ISSCC, page 348-350. IEEE, (2021)A 2Gb/s/pin 512Mb Graphics DRAM with NoiseReduction Techniques.M. Brox, H. Fibranz, M. Kuzmenka, F. Lu, S. Mann, M. Markert, U. Möller, M. Plan, K. Schiller, P. Schmölz and 7 other author(s). ISSCC, page 537-546. IEEE, (2006)

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Disambiguation of "Weller, Jörg"

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75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques.

Please choose a person to relate this publication to

Werner Jörg

Johannes-Richard Jörg

Edgar Jörg

Ole Berg Jörgensen

Erwin Jörg

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Weller, Jörg"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques.

Please choose a person to relate this publication to

Werner Jörg

Johannes-Richard Jörg

Edgar Jörg

Ole Berg Jörgensen

Erwin Jörg

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques.