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pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques.

R. Kho, D. Boursin, M. Brox, P. Gregorius, H. Hoenigschmid, B. Kho, S. Kieser, D. Kehrer, M. Kuzmenka, U. Moeller, P. Petkov, M. Plan, M. Richter, I. Russell, K. Schiller, R. Schneider, K. Swaminathan, B. Weber, J. Weber, I. Bormann, F. Funfrock, M. Gjukic, W. Spirkl, H. Steffens, J. Weller, and T. Hein. ISSCC, page 134-135. IEEE, (2009)

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Peter Kehrer

Colin Kehrer

Ulf Kehrer

Christiane Kehrer

Gerhard Kehrer

Other publications of authors with the same name

A 20 Gb/s 82mW one-stage 4:1 multiplexer in 0.13 μm CMOS.D. Kehrer, and H. Wohlmuth. ESSCIRC, page 385-388. IEEE, (2003)Cascading Techniques for a High-Speed Memory Interface.Z. Gu, P. Gregorius, D. Kehrer, L. Neumann, E. Neuscheler, T. Rickes, H. Ruckerbauer, R. Schledz, M. Streibl, and J. Zielbauer. ISSCC, page 234-599. IEEE, (2007)A 30-gb/s 70-mW one-stage 4: 1 multiplexer in 0.13-μm CMOS.D. Kehrer, and H. Wohlmuth. IEEE J. Solid State Circuits, 39 (7): 1140-1147 (2004)A 15 GHz 256/257 dual-modulus prescaler in 120 nm CMOS.H. Wohlmuth, and D. Kehrer. ESSCIRC, page 77-80. IEEE, (2003)A 24 GHz dual-modulus prescaler in 90nm CMOS.H. Wohlmuth, and D. Kehrer. ISCAS (4), page 3227-3230. IEEE, (2005)A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques.R. Kho, D. Boursin, M. Brox, P. Gregorius, H. Hoenigschmid, B. Kho, S. Kieser, D. Kehrer, M. Kuzmenka, U. Moeller and 16 other author(s). IEEE J. Solid State Circuits, 45 (1): 120-133 (2010)A monolithic 2.45 GHz, 0.56 W power amplifier with 45% PAE at 2.4 V in standard 25 GHz fT Si-bipolar.W. Bakalski, W. Simbürger, D. Kehrer, H. Wohlmuth, M. Rest, and A. Scholtz. ISCAS (4), page 803-806. IEEE, (2002)A low power 13-Gb/s 2^7-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS.H. Wohlmuth, and D. Kehrer. SBCCI, page 233-236. ACM, (2004)Modeling of monolithic lumped planar transformers up to 20 GHz.D. Kehrer, W. Simbürger, H. Wohlmuth, and A. Scholtz. CICC, page 401-404. IEEE, (2001)75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques.R. Kho, D. Boursin, M. Brox, P. Gregorius, H. Hoenigschmid, B. Kho, S. Kieser, D. Kehrer, M. Kuzmenka, U. Moeller and 16 other author(s). ISSCC, page 134-135. IEEE, (2009)

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Disambiguation of "Kehrer, Daniel"

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75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques.

Please choose a person to relate this publication to

Peter Kehrer

Colin Kehrer

Ulf Kehrer

Christiane Kehrer

Gerhard Kehrer

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Kehrer, Daniel"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques.

Please choose a person to relate this publication to

Peter Kehrer

Colin Kehrer

Ulf Kehrer

Christiane Kehrer

Gerhard Kehrer

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques.