( en | de | ru )

 

Disambiguation of "Koyanagi, Mitsumasa"

Author of the publication

copydeleteadd this publication to your clipboard
Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory.

, , , , , , , and . 3DIC, page 1-4. IEEE, (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Koyanagi, Mitsumasa
add a person with the name Koyanagi, Mitsumasa
 

Other publications of authors with the same name

Future system-on-silicon LSI chips., , , , , and . IEEE Micro, 18 (4): 17-22 (1998)Cu-Cu Direct Bonding Through Highly Oriented Cu Grains for 3D-LSI Applications., , , , , , , and . 3DIC, page 1-4. IEEE, (2021)Copper Electrode Surface Features and Cu-SiO2Hybrid Bonding., , , , , and . 3DIC, page 1-4. IEEE, (2023)High density Cu-TSVs and reliability issues., , , , and . 3DIC, page 1-4. IEEE, (2011)Stacked SOI pixel detector using versatile fine pitch μ-bump technology., , , , and . 3DIC, page 1-4. IEEE, (2011)3D memory chip stacking by multi-layer self-assembly technology., , , , , , , , and . 3DIC, page 1-4. IEEE, (2013)Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature., , , , , , and . 3DIC, page 1-5. IEEE, (2010)High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs., , , , , and . 3DIC, page 1-4. IEEE, (2011)A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface., , , , , , , , , and 45 other author(s). ISSCC, page 422-424. IEEE, (2012)Three-dimensional integration technology and integrated systems., , and . ASP-DAC, page 409-415. IEEE, (2009)