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Disambiguation of "Hedayati, Hiva"

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A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET.

, , , , , , , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)

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Mina Hedayati

Mehdi Keshavarz Hedayati

Mehdi Keshavarz Hedayati

Kerstin Khalaj Hedayati

Eskandar Khaladj Hedayati

 

Other publications of authors with the same name

3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver., , , , , , , , , and 2 other author(s). ESSCIRC, page 250-253. IEEE, (2018)A 3 GHz Wideband Σ Δ Fractional-N Synthesizer With Switched-RC Sample-and-Hold PFD., and . IEEE Trans. Very Large Scale Integr. Syst., 20 (9): 1681-1690 (2012)A 1MHz-bandwidth type-I ΔΣ fractional-N synthesizer for WiMAX applications., , and . ISSCC, page 390-391. IEEE, (2009)3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET., , , , , , , , and . ISSCC, page 68-70. IEEE, (2016)A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 52 (4): 1101-1110 (2017)A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET., , , , , , , , and . IEEE J. Solid State Circuits, 51 (12): 3167-3177 (2016)A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET., , , , , , , , , and 4 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A 1 MHz Bandwidth, 6 GHz 0.18 µm CMOS Type-I ΔΣ Fractional-NSynthesizer for WiMAX Applications., , and . IEEE J. Solid State Circuits, 44 (12): 3244-3252 (2009)Correction to Ä 1 MHz Bandwidth, 6 GHz 0.18 μ m CMOS Type-I Delta Sigma Fractional-N Synthesizer for WiMAX Applications" Dec 09 3244-3252., , and . IEEE J. Solid State Circuits, 45 (6): 1256 (2010)